nVIDIA Corporation and Tharas Systems to Deliver Joint Technical Presentation at Synopsys User's Group Meeting
—(BUSINESS WIRE)——
Tharas Systems:
Topic
Verification of GeForce 6800 series of Graphic Processor Units
with VCS Simulation and Hammer Hardware Acceleration
Presenters
Ramesh Narayanaswamy, vice president of Engineering at Tharas
Systems, Inc.
Narendra Konda, verification manager at nVIDIA Corporation.
Abstract
This paper describes the methodology required to achieve the best
performance with Synopsys' VCS Verilog Simulator and Tharas Systems'
Hammer Hardware Accelerator on a large design verification project.
The methodology was developed by nVIDIA's Verification team. It is a
collection of coding style recommendations for Design/Verification
objects such as PLLs, Monitors, etc. The potential benefits of each
technique are discussed in the paper.
Time & Location
Wednesday, March 16, 2005 at 9:00am at the Santa Clara Marriott
Hotel, 2700 Mission College Boulevard, Santa Clara, CA 95054.
SNUG Interoperability Fair
Tharas will also demonstrate its industry proven, custom-processor
based, hardware-assisted verification platform at the SNUG
Interoperability Fair to be held at Santa Clara Marriot Hotel on March
15, 2005 from 5:00pm-7:30pm.
About Presenters
Ramesh Narayanaswamy is a co-founder and vice president of
Engineering at Tharas Systems. Earlier he was an EDA methodology
consultant at SGI, and a director of software at Zycad where he
developed and helped deploy simulation accelerators at Intel, AMD,
IBM, LSI Logic and Toshiba Corporation.
Narendra Konda is a verification manager at nVIDIA responsible for
the management of all hardware-assisted verification projects. Prior
to nVIDIA, he worked at 3dfx Interactive and Quickturn Design Systems.
Mr. Konda holds a M.S. in Electrical Engineering from Portland
University.
About Tharas Systems
Tharas Systems develops and markets custom processor-based
hardware accelerators for system-on-chip design and verification. Its
high-performance verification technology leads to a significant
shortening of the verification cycle and material reduction in
time-to-market for designers of complex integrated circuits and
electronic systems. Tharas' custom-processor based hardware-assisted
verification solution works in conjunction with popular Verilog and
VHDL-based software simulators from Cadence Design (NYSE:CDN), Mentor
Graphics (Nasdaq:MENT), and Synopsys (Nasdaq:SNPS). Tharas Systems is
located in Santa Clara, California, and has regional sales and support
offices in Southern California, Texas and Japan. Customers include
communications, computer, networking and semiconductor companies. For
more information visit: http://www.tharas.com.
Hammer(R) is a trademark of Tharas Systems Inc. Tharas
acknowledges trademarks or registered trademarks of other
organizations for their respective products and services.
Contact:
Tharas Systems, Inc.
Sanjay Sawant, 408-855-3207
sanjay@tharas.com
